The present invention provides moisture and/or ion barriers that are capable of protecting silicon devices and wiring, e.g. Cu wiring, found in chip level interconnects from moisture and/or ions. Specifically, the present invention utilizes polymeric compounds such as hydrocarbons and fluoropolymers as a moisture and/or ion barrier layer and has found that such polymeric compounds inhibit the penetration of water and/or metal ions into integrated circuit (IC) interconnect structures and silicon devices. The polymeric barrier layer of the present invention replaces the inorganic barrier layers that are currently employed in the semiconductor industry for protecting such structures and devices. The polymeric barrier layer of the present invention can be used for frontside as well as backside protection of silicon devices. The present invention also provides IC interconnect structures which contain the polymeric barrier layer of the present invention. As stated above, the polymeric barrier layer of the present invention can be found on the frontside as well as the backside of the structure.
Presently in IC manufacturing, the wiring in chip level interconnects and the device itself are normally protected from moisture by various layers of inorganic dielectrics consisting of oxides or nitrides such as silicon nitride and/or silicon oxide. In addition to being effective as moisture barrier layers, inorganic dielectrics are also excellent barriers against the migration of ions which can be present as contaminants or in processing fluids such as etching solutions. Such ions may corrode the metal wiring as well as migrate to the semiconductor itself wherein the migrating ions may form fast moving suicides which essentially destroy the semiconductor device.
A portion of a typical prior art IC chip containing inorganic barrier layers is shown in FIG. 1. Specifically, FIG. 1 comprises substrate 10 composed of a processed semiconductor material such as Si which contains active device regions such as transistors (not shown in the drawing). On top of substrate 10 are one or more inorganic interconnect levels 12 (only one is shown in the drawings) which contain vias 14, metal lines 16 and metallic pads 18. Todays advanced chips typically have 6-8 levels of metal wiring and thus of dielectric levels. The inorganic interlevel interconnect is capped off by two layers consisting of a silicon nitride (Si3N4) layer 22 on top of a silicon dioxide (SiO2) layer 20. A polymer layer 24 composed of a polyimide, for example, is usually applied on top of the capping layers as a scratch guard and stress buffer layer. Capping layers 20 and 22 and polymer layer 24 are opened down to metallic pads 18 so as to allow a connection from the chip interconnect structure to the next level electronic package. The connection is made either by solder balls, C4 (Controlled Collapse Chip Connection) technology or another connection technology such as wire bonding or TAB bonding. The structure shown in FIG. 1 contains a C4 solder ball 26.
Despite being successfully employed as barrier layers in IC interconnect structures, inorganic dielectrics such as SiO2 and Si3N4, i.e. capping layers 20 and 22, are very brittle. The brittleness is the main problem because the organic dielectrics have higher expansion coefficients and the stress caused by expansion can crack the capping layer. The dielectric constant is the reason why organic dielectrics are used as interlevel dielectrics. Thus, much research endeavor has been applied in developing interlevel dielectrics which are based on organic polymers such as polyimides, polybenzocyclobutanes (BCBs) and poly(arylene ethers). These organic dielectric materials have a lower dielectric constant than inorganic materials like SiO2 and thus reduce signal delays. While organic dielectric materials can exhibit sufficiently low dielectric constants, they tend to be permeable to moisture and other contaminants. This permeability problem is particularly detrimental to Cu wiring which can oxidize in the presence of moisture. In addition, ions such as iron, copper, sodium, and/or potassium ions among others can corrode the Cu wiring. Furthermore, ions such as iron and copper can potentially migrate to the semiconductor where they form fast moving suicides which may destroy the device.
A typical prior art structure that contains an interlayer dielectric made from an organic polymer is shown in FIG. 2. Specifically, FIG. 2 comprises substrate 30 composed of a processed semiconductor material such as Si which contains active device regions such as transistors (not shown in the drawings). On top of this device level is an organic interconnect level 32 which contains vias 34, metal lines 36 and metallic pads 38. The organic interconnect level may comprise several layers of organic dielectric materials. Specifically, the organic interconnect level is composed of a low dielectric constant organic material which is capped by three layers of inorganic materials consisting from bottom to top of a Si3N4 layer 40, a SiO2 layer 42 and a layer of Si3N4 44. Capping layers 40, 42 and 44 serve as a moisture and/or ion barrier for the low dielectric constant material below. A polymer layer 46 composed of a polyimide, for example, is usually applied on top of capping layers 40, 42 and 44 as a scratch guard/stress buffer layer. Capping layers 40, 42 and 44 and polyimide layer 46 are opened to expose metallic pads 38 and then a connection from the chip interconnect structure to the next level electronic package is made either by solder balls, C4 (Controlled Collapse Chip Connection) technology, or another connection technology such as wire bonding or TAB bonding. In FIG. 2, the connection is made by utilizing C4 solder ball 48.
The production of the aforementioned capping layers in FIG. 2 requires extra processing steps. Furthermore, these capping layers are rather brittle and can easily be cracked by thermal expansion of the underlaying organic dielectric material.
In view of the drawbacks mentioned hereinabove concerning the use of organic dielectric interlevels and thus the need for inorganic capping layers, there is a need to provide a flexible barrier layer which is compatible with the organic dielectric interlayer and prevents moisture and/or ions from penetrating to the Cu wiring of such IC interconnect structures or to the semiconductor device itself.
One object of the present invention is to provide a moisture/ion barrier layer which is compatible with the low dielectric organic material found in the interconnect level which serves to protect wiring, e.g. Cu wiring, and the semiconductor substrates of ICS and other interconnect structures.
Another object of the present invention is to provide a moisture/barrier layer which replaces the inorganic barrier layers found in prior art IC interconnect structures like the kind illustrated in FIG. 2 and if applied after the chips are diced from the wafer, the moisture/barrier layer can protect the sidewalls of the diced edge.
A further object of the present invention is to provide a method of providing such a moisture/ion barrier layer so that the two above objectives are met.
These and other objects and advantages are achieved in the present invention by utilizing a polymeric barrier layer that comprises either a fluoropolymer, a polychlorofluoropolymer or a hydrocarbon. The hydrocarbon barrier layer can be aromatic, aliphatic or aromatic/aliphatic. The polymeric barrier layer of the present invention replaces the inorganic capping layers that are typically present in prior art IC interconnect structures.
Specifically, the present invention provides interconnect structures which comprise an active device containing semiconductor substrate; an organic dielectric interconnect structure on top of said substrate, wherein said organic dielectric interconnect structure contains metallic vias, lines and pads embedded in one or more layers, where said metallic pads serve to make contact with a next level package by means of solder balls, wire bonding or TAB connections; a polymer scratch guard/stress buffer layer on said organic dielectric interconnect structure; and a polymeric barrier layer on said polymer scratch/stress buffer layer, wherein said polymeric barrier layer comprises a fluoropolymer, a polychlorofluoropolymer or a hydrocarbon.
Another aspect of the present invention relates to a method of forming a polymeric barrier layer on an interconnect structure. Specifically, the method of the present invention comprises forming a polymeric barrier layer on at least the frontside (business side) of a previously fabricated IC interconnect structure, wherein said polymeric barrier layer comprises a fluoropolymer, a polychlorofluoropolymer or a hydrocarbon.
Another aspect of the present invention relates to a method of protecting the diced edge of a chip from ion and moisture ingress by applying the inventive polymeric barrier layer to semiconductor dies after dicing. This will coat the now exposed edges and prevent contamination of the dielectric and wires, wherein said polymeric barrier layer comprises a fluoropolymer, polychlorofluoropolymer or a hydrocarbon.
Another aspect of the present invention relates to a method of protecting the backside of the semiconductor from ionic or metallic contamination which is able to form mobile silicides. This is accomplished in the present invention by providing the inventive polymeric barrier layer to the backside of the structure.